1. Field of the Invention
The present invention relates to a wiring substrate and a semiconductor device. More particularly, the present invention relates to a wiring substrate including a wiring substrate main body, a wiring pattern having connection portions to which a semiconductor element is flip-chip bonded, a solder resist from which the connection portions are exposed, and a dam provided on the solder resist to block a underfill resin provided in a clearance between the semiconductor element and the wiring substrate main body, and a semiconductor device having the wiring substrate.
2. Description of Related Art
As a semiconductor device, there is a semiconductor device including a wiring substrate main body, a wiring pattern having connection portions to which a semiconductor element is flip-chip bonded, a solder resist from which the connection portions are exposed, an underfill resin provided in a clearance between the semiconductor element and the wiring substrate main body, and a dam provided on the solder resist to block the underfill resin (see FIG. 1).
FIG. 1 is a plan view of a semiconductor device of the related art. FIG. 2 is a sectional view of the semiconductor device shown in FIG. 1.
Referring to FIG. 1 and FIG. 2, a semiconductor device 200 of the related art includes a wiring substrate 201, a semiconductor element 202, an underfill resin 203, and external connection terminals 204.
The wiring substrate 201 has a wiring substrate main body 211 having a semiconductor element mounting area J in which the semiconductor element 202 is mounted, a wiring pattern 212, internal connection pads 214, a solder resist 216, a dam 217, and external connection pads 219.
The wiring substrate main body 211 is constructed by a plurality of insulating layers, vias and wirings formed in a plurality of insulating layers, and the like. The vias and the wirings provided on the wiring substrate main body 211 electrically connect the wiring pattern 212, the internal connection pads 214, and the external connection pads 219.
The wiring pattern 212 is provided on a portion of an upper surface 211A of the wiring substrate main body 211 corresponding to the semiconductor element mounting area J. The wiring pattern 212 has connection portions 222 to which a bump 209 is connected respectively.
The internal connection pads 214 are provided in an area of the upper surface 211A of the wiring substrate main body 211, which is positioned outside the semiconductor element mounting area J. The internal connection pads 214 are the pads that are electrically connected to a wiring substrate 206, on which an electronic component 207 is mounted, via an internal connection terminal 208.
The solder resist 216 is provided on the upper surface 211A of the wiring substrate main body 211. The solder resist 216 has opening portions 224, from which an upper surface of the internal connection pad 214 respectively, and an opening portion 225, which is formed to have a size substantially equal to the semiconductor element mounting area J when viewed from the top. The opening portion 225 is provided so as to penetrate a portion of the solder resist 216 corresponding to the semiconductor element mounting area J. Accordingly, the opening portion 225 exposes the wiring pattern 212 in the portion arranged in the semiconductor element mounting area J.
The dam 217 is provided on the solder resist 216 so as to surround the semiconductor element mounting area J. The shape of the dam 217 is a frame. The dam 217 blocks the underfill resin 203 such that, when the underfill resin 203 provided in a clearance between the wiring substrate 201 and the semiconductor element 202 is formed, the underfill resin 203 does not flow out to the internal connection pads 214. A distance M between an inner wall of the opening portion 225 of the solder resist 216 or an end portion of semiconductor element 202 and an inner wall of the dam 217 is set constant around a whole circumstance of the dam 217. The distance M can be set to 1.1 mm to 1.5 mm, for example. Also, a height of the dam 217 M can be set to 20 μm, for example.
The external connection pads 219 are provided on a lower surface 211B of the wiring substrate main body 211. The external connection pads 219 are used to provide the external connection terminals 204, which are connected to a mounting substrate (not shown) such as a mother board, or the like, respectively.
The semiconductor element 202 is flip-chip bonded to the connection portions 222. Concretely, the semiconductor element 202 is electrically connected to the connection portions 222 via the bumps 209 provided on electrode pads 226 of the semiconductor element 202, respectively. Lower ends of the bumps 209 are connected to the connection portions 222.
The underfill resin 203 prevents deterioration of reliability of the wiring pattern 212. That is, the underfill resin 203 improves a joining strength of connection portions between the bumps 209 and the connection portions 222, and also suppresses a occurrence of corrosion of the wiring pattern 212.
After the semiconductor element 202 is mounted on the wiring substrate 201, the underfill resin 203 is formed as follows. First, nozzles (not shown) for feeding the under fill resin are arranged so as to oppose to a groove 231. Here, the groove 231 is formed at underfill resin feeding area K and between an outer peripheral end of the semiconductor element 202 and an inner wall of the dam 217 (also see FIG. 1). Then, the underfill resin is fed from the nozzles while moving the nozzles as shown in allows N shown in FIG. 1. Thus fed underfill resin spreads over an interior of the inner circumference of the dam 217, reaches to an opposite corner of a corner where the underfill resin feeding area K and thus the underfill resin 203 is formed.
The external connection terminals 204 are provided on lower surfaces of the external connection pads 219. The external connection terminals 204 are the terminals that are connected to the mounting substrate (not shown) such as the mother board, or the like (see Japanese Patent Unexamined Publication JP-A-2006-351559, for example).
FIG. 3 is a plan view explaining the problem arisen in the semiconductor device of the related art, and FIG. 4 is a sectional view of the semiconductor device shown in FIG. 3. In FIG. 3 and FIG. 4, the same reference symbols are affixed to the same constituent portions as those of the semiconductor device 200 shown in FIG. 1 and FIG. 2 of the related art.
In the semiconductor device 200 of the related art, when a size of the surface of the semiconductor element 202 is increased (concretely, when a size of the semiconductor element 202 when viewed from the top is more than 10 mm square), an area P in which the underfill resin 203 is not filled is formed. The area P is in a clearance between a corner portion 202B of the semiconductor element 202 and the wiring substrate 201, which is positioned on the opposite side to a corner portion 202A of the semiconductor element 202 surrounded with the underfill resin feeding area K. Therefore, the wiring pattern 212 provided on the portion corresponding to this area P is not covered with the underfill resin 203. As a result, corrosion, electromigration and etc. are caused and thus reliability of the wiring pattern 212 is lowered.